I. Field of the Invention
The invention generally relates to digital filters and in particular to digital filters for use in mobile telephones.
II. Description of the Related Art
Some digital mobile telephones, such as CDMA telephones, employ digital filters for performing low bandpass filtering to eliminate noise and other interference from a received signal. FIG. 1 illustrates pertinent receive components of an exemplary mobile telephone 10.
A signal carrying, for example, encoded speech is received by antenna 12, downconverted to a baseband and amplified, if necessary, by receiver 14 then routed through an analog-to-digital converter (ADC) 15 for conversion to discrete samples. The discrete samples are routed through a digital filter 16 to be described in greater detail below which filters out frequencies below a selected threshold. The threshold is selected to distinguish between information components of the transmitted signal and noise and other interference components. The signals are then demodulated by a demodulator 18 and decoded by a signal decoder 20. Output signals from the signal decoder are routed to a speech decoder 22 for conversion to digitized voice signals. The digitized voice signals are converted to analog signals by a digital to analog converter (DAC) 24 for ultimate output through a speaker 26 of the mobile telephone. Other components, such as error detection and correction components, may be provided as well within the receive portion of the mobile telephone.
As noted, the digital filter is employed for low-pass filtering of the received digitized samples. The operation of a generic digital filter is represented by the transform equation of FIG. 2 wherein a discrete input signal x(n) is filtered by a transfer function H(z) 28 into a discrete output signal y(n). The output signal and transfer function may be represented mathematically by: ##EQU1##
A finite implementation of the generic filter is set forth in FIG. 3 for a filter employing M filter coefficients A group of M z.sup.-1 delay elements 30 generate successively delayed versions of an x(n) input signal. The input signal and each delayed version are routed through multipliers 32 for multiplication against respective filter coefficients h.sub.0 -h.sub.M-1. The results are summed by a set of adders 34, held in a register 36, then output as y(n). As can be seen, the filter of FIG. 3 performs the summation of Equation (1) for k=0 to M-1.
For the exemplary implementation of the mobile telephone of FIG. 1, digitized signals are received by the digital filter at about 120 thousand samples per second (ks/sec). If the digital filter were implemented as set forth in FIG. 3, considerable energy would be expended by the adders and multipliers. For mobile telephones, which typically employ a rechargeable battery power source, it is critical that the amount of power consumed by the telephone be minimized to ensure sufficient operating time before recharging is necessary. One technique for reducing the amount of power consumed by the adders and multipliers of the digital filter is to implement it as a polyphase decimating filter wherein the adders and multipliers operate at only a fraction of the rate of the input signals. In the most popular of semiconductor technologies CMOS, the relationship between power and frequency is linear. So reducing the rate of operation (clock frequency) of a circuit directly reduces power consumption.
In this regard, the aforementioned transfer function may be rewritten as follows: EQU H(z)=E.sub.0 (z)+z.sup.-1 E.sub.1 (z)+z.sup.-2 E.sub.2 (z) Eq.(3)
where ##EQU2##
For a finite implementation employing fourteen filter coefficients, E.sub.0 (z), E.sub.1 (z) and E.sub.2 (z) are approximated as: EQU E.sub.0 (z).congruent.h.sub.0 +h.sub.3 z.sup.-3 +h.sub.6 z .sup.- +h.sub.9 z.sup.-9 +h.sub.12 z.sup.-12 EQU E.sub.1 (z).congruent.h.sub.1 +h.sub.4 z.sup.-3 +h.sub.7 z.sup.-6 +h.sub.10 z.sup.-9 +h.sub.13 z.sup.-12 EQU E.sub.2 (z).congruent.h.sub.2 +h.sub.5 z.sup.-3 +h.sub.8 z.sup.-6 +h.sub.11 z.sup.-9 Eq.(5)
Hence, the transfer function H(z) may be decomposed into three separate E(z) transfer functions to provide a three-phase decimating filter. FIG. 4 symbolically illustrates the resulting three-phase filter which employs three decimating units 40 along with three E(z) transfer function units 42, 43, and 44 corresponding to E.sub.0 (z), E.sub.1 (z) and E.sub.2 (z) respectively. The filter provides an output signal y(n) at a rate that is one third of the rate of an input signal x(n). With this decimating filter implementation, power is saved within the filter because:
a) Lower frequency of operation results directly in lower power dissipation for CMOS technology, PA1 b) lower frequency adder and multiplier components may be employed.
Therefore their implementations may contain fewer logic gates, translating to smaller parasitic capacitances and therefore reduction on their power dissipation. Moreover, other components of the mobile telephone that receive the filtered signal, such as the decoder and demodulator described above, may operate at lower frequencies as well thereby saving further power.
FIG. 5 illustrates one possible implementation of a three phase filter 100. Three groups or stages of sub-filters are provided with each group having Z.sup.-3 delay elements 130, multipliers 132, and adders 134. Delay elements 130 may be implemented as latches enabled by a clock signal (not shown) operating at one third of the rate of the input signal x(n). For example, delay elements 130 may be operated at 40 kHz for an input signal having 120 ks/sec. Hence, multipliers 132 and adders 134 likewise operate at 40 kHz rather than 120 kHz thereby consuming less power. To offset the signals input to the three stages of the filter, additional Z.sup.-1 delay elements 140 are provided, each enabled by a clock signal operating at the rate of the input signal. As a result, for an input stream comprising samples x.sub.1, x.sub.2, x.sub.3, x.sub.4, x.sub.5, x.sub.6, etc., the first row of multipliers and adders processes x.sub.3, x.sub.6, x.sub.9, etc., the second row of multipliers and adders processes x.sub.2, x.sub.5, x.sub.8, etc., and the third row of multipliers and adders processes x.sub.1, x.sub.4, x.sub.7, etc. Coefficients for applying to the multipliers are distributed as shown such that the filters perform the mathematical operations of Equation (5) above, to thereby evaluate E.sub.0 (z), E.sub.1 (z) and E.sub.2 (z). (In this regard, initially, h.sub.0 is multiplied by x.sub.3, h.sub.1 by x.sub.2 and h.sub.2 by x.sub.1. Then, h.sub.0 is multiplied by x.sub.6, h.sub.1 by x.sub.5 and h.sub.2 by x.sub.4 while h.sub.3 is multiplied by x.sub.3, h.sub.4 by x.sub.2 and h.sub.5 by x.sub.1 etc.) Additional adders 142 and 144 add the outputs of the three rows together for latching in a final register 146 which is enabled by the one-third rate clock signal to thereby output y(n) at a rate one third that of x(n). Hence, one output signal y(n) is generated during every three cycles of the input signal x(n).
Hence, the three-phase polyphase filter of FIG. 5 uses less power than a single phase implementation and is therefore desirable for use in a mobile telephone or similar device operating from a limited power supply. However, room for improvement remains. As described, a separate multiplier and adder is required in connection with each delay element of each row of the filter. The many multipliers and adders each require numerous logic gates and are thereby expensive both in terms of circuit space and in terms of design, manufacturing and reliability costs. Circuit space and cost are both important factors in mobile telephones and similar devices which are preferably as small and as inexpensive as possible.
Accordingly it would be desirable to provide a polyphase digital filter which has the power saving advantages of a polyphase filter but which requires fewer multipliers and adders and is thereby smaller and more cost effective. It is to that end that aspects of the present invention are primarily directed.